| 1. | Bit status register
位状态寄存器 |
| 2. | Csr information technology - microprocessor systems - control and status registers architecture for microcomputer buses
信息技术.微处理机系统.微机总线用控制与状态寄存器 |
| 3. | A method of inte * * cing with hardware that involves repeatedly reading a status register until the device has reached the awaited state
一种硬件交互方法，不断读状态寄存器，直到设备进入等待状态。 |
| 4. | A method of interfacing with hardware that involves repeatedly reading a status register until the device has reached the awaited state
一种硬件交互方法，不断读状态寄存器，直到设备进入等待状态。 |
| 5. | Csr information technology - microprocessor systems - control and status registers architecture for microcomputer buses same as iso iec 13213 - 1994
信息技术.微处理机系统.微处理机总线的控制和状态登记 |
| 6. | Information technology - microprocessor systems - control and status registers architecture for microcomputer buses same as iso iec 13213 - 1994
信息技术.微处理器系统.微处理机总线的控制和状态登记体系结构 |
| 7. | Qe1 achieve the whole synchronization by software and hardware . during the course of the initialization of the qe1 system , the chip pm4354 can accomplish the task of synchronization of bit , frame and multiframe after the chip initialization by the software . after pm4354 accomplishes the bit synchronization , qel will read the status registers of the pm4354 to get the status of each el circuit and choose recovered clock of the specified the el circuit as the external timing source of the whole htc - 5200an equipment
Qe1系统在系统初始化时，通过软件完成对硬件芯片pm4354的初始化工作后，便可利用该芯片完成4路e1的同步(位同步、帧同步和复帧同步) ；在pm4354完成时钟提取的任务后， qe1通过不断地访问pm4354的状态寄存器，获得每路e1的状态信息，在时钟源的选择原则下，选择指定e1线路的恢复时钟作为整个htc - 5200an节点设备的外部参考时钟，从而解决了htc 5200an的中继板卡由e1变为qe时所带来的网同步时钟源。 |
